·       Compliant with QSFP+ MSA Specification

·       4x10Gbps 850nm VCSEL-based Transmitter

·       Maximum Link Length of 150m Via OM3 Multimode Fiber(MMF)

·       Wide Operating Temperature: 0°C to +70°C

·       RoHS and FCC compliant

Absolute Maximum Ratings

Recommended Operating Conditions

Optical Characteristics(T=25°C, unless note)

Electrical Characteristics

 
Digital Diagnostic Function

ASCENT’s QSFP-40-SR4-01 supports the 2-wire serial communication protocol as defined in the QSFP+ MSA, which allows real-time access to the following operating parameters:

·      Transceiver temperature

·      Laser bias current

·      Transmitted optical power

·          Received optical power

·         Transceiver supply voltage

It also access and monitor module information (ex: Media type, Vendor name, Part Number, Serial Number, Wavelength, Voltage, temperature, etc), provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range.

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP+ transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP+ devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in below figure-QSFP+ Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID. information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in below figure upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.

For more detailed information including memory map definitions, please see the QSFP+ MSA Specification.